October 31, 2025
Hex flex vs head-scratches
x86 architecture 1 byte opcodes
x86 opcode cheat sheet drops — geeks cheer, newbies cry, sizecoders party
TLDR: A compact x86 opcode map dropped, showcasing one‑byte instructions and quirky “do nothing” lore, and it split the crowd. Power users saw a near‑usable mini instruction set, sizecoders cheered, and newcomers were baffled—asking what “0Eh” even means—proving low‑level code is equal parts magic and migraine.
A wall-of-hex just hit the timeline: a dense cheat sheet of one‑byte x86 opcodes (aka the tiny building blocks computers use to do stuff). It’s like someone dumped ancient CPU runes on the table—ADD here, MOV there, mysterious notes about “NOP” (a do‑nothing instruction) and 8086-era secrets—and yelled, “Good luck!” Cue chaos. The community instantly split. One camp squinted at the hieroglyphs, with GeorgeTirebiter sighing, “I don’t understand,” while another camp flexed hard. Sharlin swaggered in with the bold take: this is almost a complete little instruction set by itself—just toss in a couple ways to touch memory and maybe immediates (numbers baked into the code)—and boom, compiler time. The sizecoding crowd (fans of ultra‑tiny programs) showed up like it’s a LAN party, with GuB‑42’s “Hello sizecoders ;)” and handy links to DOS tips and a deep‑dive PDF. Meanwhile, a mini‑mystery brewed: “What does the 0eh comment mean?” asked hornd, speaking for everyone pretending they didn’t also Google it. The spiciest subplot? The “NOP lore,” with notes on the oddball history of XCHG‑as‑NOP and how a REP prefix turns NOP into PAUSE on modern chips. Nerds are thrilled; the rest of us are dizzy—and entertained.
Key Points
- •The article catalogs x86 one-byte opcodes, listing mnemonics and operand forms for arithmetic, logic, data movement, string, I/O, and control-flow instructions.
- •Grouped opcodes (e.g., group #2, #3, #11) and multiple instruction forms are identified using ModRM and size annotations (b/v, Ib/Iz).
- •Prefix behavior is documented, including LOCK, REP/REPNE, segment overrides (ES/SS/FS/GS), and operand/address-size prefixes.
- •Notes clarify 0x90 (XCHG AX/EAX/rAX, rAX) as NOP across modes, with REP able to apply PAUSE semantics if CPUID indicates support; XCHG EAX,EAX must not zero RAX upper bits in PM64 O32.
- •Extended forms and annotations (REX2, Df64/I64, REX2.W0/W1) suggest 64-bit semantics and expanded register handling; CPU-generation tags (8086–80386) indicate availability.