November 1, 2025
License fights, hardware hype
Open-Source Ada: From Gateware to Application
Ada Goes DIY: Fans cheer the chip-to-app dream, then ask “is it really open”
TLDR: AdaCore’s demo shows an open-source path from DIY chips to apps using Ada on a RISC‑V soft CPU. The crowd loves the hardware focus but immediately debates how “open” Ada really is, sparking clarifications about language vs. tools—and jokes about rockets and strict librarians policing code.
The post promises a fully open-source journey from reconfigurable chips to apps, starring the often-misunderstood language Ada as a safer rival to C. The crowd? Hyped—but immediately tangled in licensing drama. One top vibe: “This looks awesome for hardware,” followed by a chorus of “wait… is Ada itself open?” Cue a lively explainer thread separating the language (a public standard) from its compilers and toolchains, with folks pointing out that some are open, some are paid, and that gray area is what trips people up. Meanwhile, the Neorv32 soft CPU on an FPGA—think “make-your-own chip” Lego—gets props for clear docs and predictable behavior.
Then the culture war kicks in. Team Ada celebrates correctness and safety; Team C flexes speed and familiarity. Jokers revive the classic meme that Ada is “for rockets and nothing else,” while others clap back that RISC‑V—an open instruction set—plus Ada is an academic and industry match made in heaven. Skeptics nitpick the “open-source stack” claim, noting the underlying chip is still proprietary; defenders call it open enough for real learning. The best quip likens Ada to a strict librarian keeping your code tidy. For curious lurkers, this thread doubled as a beginner’s guide to Ada and RISC‑V.
Key Points
- •The article presents an open-source Neorv32 BIOS project using Ada to demonstrate a full stack from gateware to applications.
- •Neorv32 is a VHDL-based RISC‑V softcore SoC with extensive documentation, extensions, and peripherals; created by Stephan Nolting.
- •The project targets the Radiona ULX3S board with a Lattice ECP5 FPGA (85k LUT), focusing on deploying a custom BIOS.
- •Neorv32 emphasizes deterministic design via Harvard architecture, a multi-cycle model, avoidance of speculative execution, and robust safety features.
- •Key features include a hardware RISC‑V debug module for on-chip debugging and support for atomic operations for concurrency.