December 6, 2025
Silicon, solder, and spilled tea
Z2 – Lithographically fabricated IC in a garage fab
Garage kid builds a 'baby Intel' chip — awe, 'old news', and investor rumors
TLDR: A college maker built a working DIY chip in his garage with a 10×10 transistor array, echoing early Intel-era tech. Comments split between awe, “this was 2021,” investor rumors about Atomic Semi, and a sudden politics detour — but everyone agrees it’s a jaw-dropping leap for at-home chipmaking.
Move over billion‑dollar cleanrooms — a college senior just cooked up a tiny, working computer chip in his garage, and the internet is losing it. Maker legend Sam Zeloof unveiled his second homemade chip: a 10×10 test array of transistors on old‑school tech, like an early Intel. He even laid parts out in Photoshop, and it runs on low voltages instead of bulky batteries. Fans called it “garage‑to‑genius” energy and compared it to building a “baby Intel” at home.
But the comments didn’t stay wholesome for long. Hype surged when someone dropped a link to Atomic Semi with the spicy whisper that “Jim Keller is investing,” turning the thread into Silicon Valley rumor hour. Then a reality check hit: a user pointed out this project’s from 2021, sparking the classic repost war — is it timeless inspiration or stale news? Meanwhile, one rabbit hole dove into a post on Sam’s brother’s site about immigration, abruptly shifting the vibe from soldering irons to social hot takes. Whiplash, anyone?
Between “kid in a garage beats the odds” optimism and “guys, check the date” skepticism, the community’s unified on one thing: it’s jaw‑dropping that a human can fab over a thousand transistors on a slice of silicon at home. Cue the memes: “Photoshop Engineer,” “parents’ garage vs $10B fab,” and “Intel 4004 vibes.”
Key Points
- •Z2 is a homemade 10×10 NMOS transistor array using a 10µm polysilicon gate process similar to early Intel technology.
- •Switching from aluminum metal gate to polysilicon gate reduced threshold voltage and overlap capacitance, enabling 2.5V/3.3V logic compatibility.
- •Measured NMOS properties include Vth ≈ 1.1 V, Vgs max 8 V, Cgs < 0.9 pF, rise/fall < 10 ns, on/off ~4.3e6, and leakage ~932 pA at Vds=2.5 V.
- •The chip layout was created in Photoshop; columns share gates and rows are series-connected, akin to NAND flash, to maintain probeable pad sizes.
- •Zeloof fabricated 15 chips (~1,500 transistors), with at least one fully functional and two mostly functional; yield/variability data collection and test automation are ongoing.