December 20, 2025
Silicon, snark & starfields
Pure Silicon Demo Coding: No CPU, No Memory, Just 4k Gates
Tiny chip draws Nyan Cat with no brain — commenters lose it
TLDR: A tiny custom chip squeezes a retro demo—starfield, 3D checkerboard, Nyan Cat—into ~4k gates, outputting video and audio without a CPU or RAM. Commenters cheer the feat, argue that flip‑flops count as memory, and balk at a $2,500 add‑on for just 4KB of storage, fueling peak nerd drama.
A hobbyist crammed a full retro demo—starfield, wobbling 3D checkerboard, shadowed scroller, plus the internet’s favorite Nyan Cat—into a teeny custom chip for Tiny Tapeout. No CPU, no RAM, just flip‑flops (tiny on‑chip switches) and about 4,000 gates pushing VGA video and one‑bit audio straight out. Cue the crowd: glimshe drops a philosophy bomb—“Hardware and Software are logically equivalent”—while Dwedit nitpicks the headline with “If you have registers, it’s not ‘no memory’,” sparking a delicious semantics brawl over what “memory” even means. Others, like xphos, are pure hype: “retro architectures… simple but fun,” itching to tapeout their own. The maker admits the weird video mode looked rough on digital captures but glorious on a real CRT, which launched a flood of “CRT supremacy” jokes and “donut vs. cat” memes. Under the hood, the build used Verilator for cycle‑by‑cycle simulation and a scrappy OrangeCrab FPGA with a DIY audio hack—sigma‑delta, not fancy PWM. Then the comment section detonated: startupsfail points out a commercial add‑on—just 4KB of static RAM—for $2,500, even if it includes a Wishbone bus (a standard way for chips to talk inside). Suddenly, the community split between “pure silicon wizardry” and “paywall pixels,” and we’re here for the drama.
Key Points
- •Two ASIC demos were created for Tiny Tapeout 8, including a C64/Amiga-style intro with starfield, 3D checkerboard, wavy text, and an oscilloscope.
- •The platform has no ROM/RAM or CPU; all state is flip-flops, requiring a custom state machine generating pixels per clock.
- •Prototyping used a 1220x480, 48 MHz video mode; simulations were done via Verilator (Verilog→C++) with SDL rendering.
- •Hardware tests ran on an OrangeCrab (Lattice ECP5) FPGA with an R-2R DAC for RGB; audio used sigma-delta via a single pin and RC filter.
- •Final Skywater 130nm design used 3374 cells and 293 flip-flops, hardened via GitHub Actions and a local tool to resolve area/routing.