January 4, 2026
FPGAs, feelings, and a 100G ceiling
Corundum – open-source FPGA-based NIC and platform for in-network compute
Open-speed network card thrills, wallet chills; devs eye a “Taxi” reboot
TLDR: Corundum is an open, fast DIY-style network card design for FPGAs, topping out at 100G, with a Linux driver and rich tools. The crowd loves the power but complains about hardware cost, while buzz builds around a “Taxi” next step as the creator live-streams a rebuild.
Corundum just dropped into the chat as the open-source speed demon of network cards: a design you load onto a reprogrammable chip (FPGA) that pushes 10/25/100 gigabit speeds, with fine timing and a Linux driver. The repo is here: GitHub, with docs at docs.corundum.io. The community’s split: the hype is real, but so is the sticker shock. One hobbyist sighed that it’s “hard to use” without deep pockets—some folks only want to tinker with simple UDP (basic internet message) filtering without selling a kidney. Meanwhile the pros are drooling over the feature list and simulation tools, but nodding at the 100G ceiling.
Power users are in love: one called it “best-in-class” under 100G and even dreams of building AI tricks like PagedAttention over a specialized network method in hardware—Corundum won’t take them all the way, but it’s getting them closer. The plot twist? Creator Alex Forencich is live-streaming a rebuild, and whispers say Taxi is where new development is happening. Cue the drama: is Corundum handing the baton to Taxi? Memes flew—“hail a Taxi to 200G,” “my wallet bluescreened”—as the crowd split between dreamers and budget realists. Under the jokes, the vibe is clear: this is a rare open tool that punches at enterprise gear, but entry costs sting—even if 10/25G runs on open modules and 100G only needs a free license. Still, building it in public? Chef’s kiss, and everyone’s watching.
Key Points
- •Corundum is an open-source, high-performance FPGA-based NIC and in-network compute platform with 10G/25G/100G Ethernet and PCIe Gen 3.
- •It features a custom PCIe DMA engine, extensive queue support (1000+), RSS, MSI, checksum offloading, and native IEEE 1588 PTP timestamping with Linux driver integration.
- •Architectural design stores queue state in BRAM/URAM, supports multiple interfaces and ports with independent schedulers, enabling precise TDMA.
- •An application section provides a dedicated PCIe BAR and interfaces to integrate custom logic with the core datapath and DMA.
- •Supports numerous Xilinx and Intel boards; uses open-source verilog-ethernet MAC/PHY for 10/25G and requires Xilinx CMAC with RS-FEC for 100G on UltraScale+.