Show HN: SHDL – A minimal hardware description language built from logic gates

Tiny hardware language drops: fans want diagrams, purists shout 'EDIF', timing cops lurk

TLDR: SHDL is a tiny language to build and simulate digital circuits with Python and fast C code. Commenters are split between turning it into pretty diagrams, insisting EDIF standards matter, and asking for timing features—early signs it could be great for learning if it adds visuals and compatibility

A mini make-your-own-circuits language just hit Show HN, and the crowd instantly split into camps. SHDL lets you describe digital logic with simple text, run it via Python, and even compile to speedy C. But the plot twist? One commenter wants to turn it into the next Mermaid for circuits. “Draw it, don’t just code it,” cheered the diagram dreamers.

Then the rulebook arrived. An old-school voice waved the standards flag: EDIF (a long-standing format for wiring diagrams) is the “real deal,” implying SHDL is cute but needs to play nice with industry norms. Meanwhile, the timing police pulled up: fans love the simulator vibes, but want time delays and signal behavior spelled out, not just on/off results.

Supporters chimed in with “looks really cool,” while a mysteriously [flagged] comment became the thread’s redacted scandal, fueling the drama without saying a word. The vibe overall? Curious, playful, a little territorial. SHDL could be a classroom darling and a hobbyist power-up; but the crowd wants shiny diagrams, standard-friendly exports, and grown-up timing. If dev Rafa leans into visuals and compatibility, this tiny tool might just graduate from neat toy to buzzy teaching staple—and that’s the tea

Key Points

  • SHDL is a gate-level hardware description language with a Python driver (PySHDL) for digital circuit simulation.
  • It compiles to optimized C code and uses GCC or compatible compilers; a CLI tool (shdlc) manages compilation and builds.
  • Installation can be done via pip (pip install PySHDL), with uv recommended for using PySHDL.
  • A quick-start example shows defining a FullAdder in SHDL and simulating it in Python using the Circuit class.
  • The project provides documentation, examples, a GitHub repository, and invites feedback via issues, discussions, pull requests, and email.

Hottest takes

use this as a markup language for logic diagrams? I'm thinking something like mermaid — Lramseyer
the standard is EDIF — fspeech
is there a way to specify and simulate time delays? — bigbadfeline
Made with <3 by @siedrix and @shesho from CDMX. Powered by Forge&Hive.