February 14, 2026
Register Rumble: Silicon Soap Opera
How many registers does an x86-64 CPU have? (2020)
Counting CPU registers ignites a brawl: APX hype, ‘behind RAX’ secrets, and RISC‑V freedom
TLDR: A 2020 explainer counts x86‑64’s many tiny storage slots, spotlighting how complex PC chips are. Comments split between excitement for Intel’s APX adding more, curiosity about hidden “behind RAX” hardware, and an open‑hardware push for RISC‑V—because register counts shape speed, portability, and the industry’s next moves.
What started as a nerdy recount of x86‑64 “how many little storage slots does your CPU really have?” turned into a comment‑section cage match. The 2020 post tallies tons of registers—including those tiny sub‑pieces—racking up dozens and showing how brain‑bending the PC chip “language” (ISA) really is. People loved the detail, but the vibe quickly shifted from math class to street fight.
The loudest chant? “More registers now!” One camp is hyped about Intel’s coming APX plan to double general‑purpose slots to 32, with one user breathlessly teasing more speed and bigger benchmarks. Another commenter grounds the hype: APX is real, but let’s understand today’s baseline first—cue the link‑drop to Intel APX. Meanwhile, hardware heads demanded the juicy stuff the post didn’t cover: the secret, behind‑the‑scenes placeholders (“register renaming”) that let CPUs juggle multiple tasks—“how many are behind RAX?” became the meme of the day.
Then came the ideological twist. One voice slammed x86 and ARM as IP‑locked and cheered RISC‑V (an open design) as the people’s champion. The rest? Jokes about “register nesting dolls,” “pocket‑sized registers,” and whether sub‑register counting is like tallying every sock in your drawer. Verdict: fascinating post, but the comments are where the sparks fly.
Key Points
- •The article defines strict rules for counting x86-64 registers, including treating subregisters as distinct due to different encodings and microcode behaviors.
- •Registers present on x86-64 CPUs but unusable in long mode may be counted; microarchitectural details like shadow registers are excluded.
- •Model-Specific Registers are included only when documented and widely available; niche-vendor and undocumented MSRs are excluded, and double-counting across access mechanisms is avoided.
- •General-purpose registers (RAX–R15) and their subregisters total 68 registers when subregisters are counted separately, including high 8-bit forms (BH, CH, DH).
- •Special registers begin with the instruction pointer (RIP); EIP/IP variants are not counted separately because they share encodings and cannot be used simultaneously in the same mode.