March 3, 2026
ARMchair warfare
Arm's Cortex X925: Reaching Desktop Performance
ARM’s desktop beast lands—but readers demand Apple, power stats
TLDR: Arm’s Cortex X925 hits AMD/Intel-level desktop performance in Nvidia’s GB10, signaling ARM’s big-league moment. Commenters demand Apple comparisons, readable mobile charts, and power/efficiency data, while some warn ARM’s memory behavior could expose new software bugs—making this a win with caveats.
Arm just dropped a desktop-class rocket: the Cortex X925, a beefy core running up to 4 GHz in Nvidia’s GB10 chip, with Dell already shipping it. Reviewers say it finally hits parity with AMD and Intel’s fastest—translation: ARM can play in high-end desktops now. Cue the comments section going full reality TV.
First slam: Where’s Apple? One reader calls it “weird” to discuss a top ARM core without any M4/M5 comparison, and the thread turns into an Apple check-in. Second blow-up: the mobile chart fiasco. People on phones can’t zoom the graphs, so half the performance story is literally unreadable. Then comes the hottest take: numbers without power are just vibes. Multiple voices demand efficiency (performance-per-watt), not just speed, with one linking a Reddit roundup to fill in the gaps.
The geeky bits—like “branch prediction,” a fancy way the chip guesses the next step—got praise, but casual readers admit their eyes glazed over. And a curveball: one commenter wonders if ARM’s different memory rules could surface new software bugs, sparking a mini panic about race conditions (code that misbehaves when things happen out of order). Verdict from the crowd: impressive core, lively review—but give us Apple, bigger charts, and power numbers, or it didn’t happen.
Key Points
- •Arm’s Cortex X925, implemented in Nvidia’s GB10, is reported to match AMD Zen 5 and Intel Lion Cove performance in top desktop setups.
- •GB10 integrates ten X925 cores across two clusters, with one core at 4.0 GHz and others at 3.9 GHz; Dell uses GB10 in its Pro Max series.
- •X925 is a 10‑wide core with larger out-of-order resources than Zen 5 and L2 capacity comparable to recent Intel P-Cores.
- •Cache and reliability design: fixed 64 KB L1; L2 configurable at 2 or 3 MB; all caches use parity/ECC with configurable ECC granules (128/256-bit).
- •System and prediction: DSU‑120 interconnect with up to 32 MB L3 and 40‑bit addressing; advanced branch predictor with large BTB hierarchy and a 29‑entry return stack.