March 9, 2026
Vectors vs. Guesswork: Fight Night
RVA23 Ends Speculation's Monopoly in RISC-V CPUs
Revolution or rebrand? Commenters roast RVA23, cheer vectors, and yawn
TLDR: RISC‑V’s RVA23 now requires vector math units on every compliant chip, shifting performance toward explicit parallel work instead of guess-ahead tricks. The comments split: some call it overdue and pragmatic, while others say it’s marketing fluff or a non-event—igniting a 'revolution vs. rebrand' debate.
RISC‑V’s new RVA23 update says every compliant chip must include vector hardware—basically, the ability to crunch lots of numbers at once—so software can count on it. The article frames this as ending “speculation’s monopoly” (speculation = the chip guessing ahead), promising simpler, cooler‑running cores without losing speed. But the real fireworks? The comments.
One reader, wmf, tossed a grenade, alleging the author’s tied to chip maker Andes and snarking that pushing vectors smells like a cover for weak out‑of‑order designs. Another heavy hitter, comex, threw cold water: vectors have been standard on big‑name chips for ages, RISC‑V was just late to require them, and most code still won’t use them. Then Validark went full roast, calling the piece “a complete waste of time” and “children’s story” marketing. Ouch.
While the article talks balance—less guesswork, more do‑lots‑at‑once—commenters are split between “finally, a sane baseline” and “meh, catch‑up dressed as revolution.” Jokes flew fast: “vectors go brrr,” “CPUs get a mandatory gym membership,” and “speculation stans vs. vector enjoyers” set the mood. Big picture, this could make apps and tools lean into parallel loops and math. But the crowd’s verdict? Still out—and very, very loud. Read the piece, stay for the drama.
Key Points
- •RVA23 mandates the RISC‑V Vector Extension (RVV), making vectors a baseline capability alongside scalar execution.
- •This mandate allows scalar cores to be simpler and more predictable, with vector units handling explicit parallel work.
- •The software performance contract changes: compilers and libraries can assume RVV, focusing optimizations on vector code and reducing scalar fallbacks.
- •Hardware designers retain microarchitectural freedom (e.g., lane width, pipeline depth) while shifting area/power toward vector throughput and memory bandwidth.
- •The article contextualizes this shift with a history of speculative execution from Tomasulo and Thornton to Smith, academia, and Intel’s Pentium Pro.