March 10, 2026
Open chip, open drama
Baochip-1x: A Mostly-Open, 22nm SoC for High Assurance Applications
Open “trust chip” lands — fans swoon, crypto nerds call the crypto outdated
TLDR: Bunnie’s Baochip‑1x is a mostly‑open security microcontroller with phone‑style memory protection, built for real production. Fans applaud the transparency and ambition, while critics blast its AES masking as outdated—kicking off a bigger fight over whether openness is enough without modern, hardened crypto.
A new mostly‑open security chip just dropped, and the comments are already a battlefield. Hardware legend Bunnie unveiled Baochip‑1x, a custom 22nm silicon brain built for “high assurance” gear. Translation: it’s a tiny, serious computer with a built‑in bouncer (an MMU, the memory gatekeeper your phone has but your toaster doesn’t) so apps can’t step on each other. It runs a Rust‑based OS, includes extras like a true random number generator, and is designed to be inspected for tampering — all while being mass‑producible at TSMC.
But the community split fast. One camp is all heart‑eyes for Bunnie’s openness and track record, cheering the audacity of sneaking his processor design into a big‑league chip. The other camp slammed the crypto under the hood: commenter zachbee pointed to the chip’s AES implementation and claimed the “masking” technique is old and known to be weak, saying newer methods (like OpenTitan’s) should be used. That sparked the classic internet showdown: “Trust through transparency” vs “Show me modern crypto hygiene.”
Meanwhile, meme‑lords had a field day with the toaster analogy: “Finally, a toaster with tabs!” Fans framed it as a Snowden‑era dream come true; skeptics called it a shiny shell with 2005‑era guts. The verdict? Open silicon is here, but the crypto nitpicking is only getting started. Check the code receipts.
Key Points
- •Baochip-1x is a mostly-open, full-custom SoC built on TSMC’s 22nm process for high-assurance applications.
- •It combines a 350MHz VexRiscv CPU with an MMU and a BIO I/O processor featuring four 700MHz PicoRV32 cores, plus 4MiB RRAM and 2MiB SRAM.
- •Security features include a TRNG, cryptographic accelerators, secure mesh, glitch sensors, ECC-protected RAM, hardware key slots, and one-way counters.
- •The design continues the Betrusted initiative, draws on the Precursor FPGA SoC, targets the Xous (Rust) OS, and supports IRIS non-destructive silicon inspection.
- •The MMU is emphasized as a key differentiator for microcontroller-class devices and is argued to be composable with CHERI, PMPs, and MPUs for robust, time-tested security.