March 22, 2026
Pixels, popcorn, and Voodoo vibes
Building an FPGA 3dfx Voodoo with Modern RTL Tools
Solo dev resurrects a ’90s Voodoo card—nostalgia erupts, AI-blog shade flies
TLDR: One developer rebuilt a classic 3dfx Voodoo 1 graphics card on a reprogrammable chip, proving old-school pixels can live again. The crowd split between pure nostalgia and sharp debates—some praising the feat, others side-eyeing the write-up as AI-ish and critiquing design choices—showing preservation meets modern tool drama.
A lone coder just rebuilt a legendary ’90s 3D card—the 3dfx Voodoo 1—on an FPGA (a reprogrammable chip, think Lego for circuits). Yes, that’s a real frame from Screamer 2, and the code’s up on GitHub. Cue the internet’s favorite combo: retro joy and comment chaos. Longtime tinkerers flooded in with memories of dial-up days and driver battles, while newcomers marveled that one person could pull this off.
Nostalgia hit hard. One user recalled sprinting to a friend’s house for dial-up help and Altavista searches; another sighed that today’s slick tech lacks the goofy, loud names like “Voodoo.” Fans cheered that these cards “had no right to look that good” and said rebuilding one from scratch is peak community content. For context: the Voodoo was a fixed-function graphics chip—no fancy shaders, just hardwired tricks—now painstakingly re-created on modern tools.
Then the spice: one commenter claimed the write-up “feels LLM-generated,” which sparked side-eye and side chats, while a deep dive critic questioned the author’s register design choices (translation: is the “magic box” too magical?). Between the “Voodoo magic” crowd and the “pipeline police,” the thread turned into a popcorn-worthy mix of retro love, AI suspicion, and nerdy nitpicks—exactly the internet’s favorite flavor.
Key Points
- •An engineer implemented a working FPGA version of the 3dfx Voodoo 1 GPU using SpinalHDL, with code available on GitHub.
- •The Voodoo 1’s graphics pipeline is fixed-function and includes shading gradients, texture sampling, mipmapping, filtering, alpha clipping, depth testing, and fog.
- •A significant debugging challenge involved transparency artifacts caused by multiple small hardware-accuracy mismatches rather than a single subsystem failure.
- •Two key abstractions enabled progress: precise modeling of register semantics in SpinalHDL and netlist-aware waveform debugging with conetrace.
- •Pipeline hazards require careful handling of register writes so state changes do not affect in-flight pixels from earlier triangles.