March 23, 2026
CISC vs RISC: FPGA Fight Night
BIO: The Bao I/O Coprocessor
Raspberry Pi copycat or smarter sidekick? Hackers clash over Bao’s I/O brain
TLDR: Bunnie unveiled BIO, a lean I/O helper for his Baochip-1x after finding Raspberry Pi’s PIO bulky on programmable boards. The community split fast: some blame the FPGA clone and defend Pi’s design, others like BIO’s predictability but worry about losing PIO’s simple, one-cycle timing model—big implications for maker hardware.
Raspberry Pi’s beloved PIO just got a spicy reality check. Hardware legend bunnie introduced BIO, the I/O sidekick inside his mostly open-source Baochip-1x, built to make timing predictable by offloading input/output chores. After cloning the Pi’s PIO on a programmable chip (an FPGA), he says it hogged resources and slowed clocks, blaming PIO’s “do-everything-in-one-go” instructions. BIO goes leaner, with assembly and C examples for the curious, and there’s even an evaluation board on Crowd Supply. Curious? The earlier chatter is here: HN.
The comments? A popcorn bucket. One camp, led by a very spicy take, claims the FPGA clone is the real villain and that “real” chips would run PIO just fine—cue the FPGA vs. ASIC (programmable chips vs. custom silicon) steel cage match. The old-school CISC vs. RISC (complex vs. simple instructions) flame war flares up, with fans praising PIO’s “one instruction per cycle” clarity while others cheer BIO’s simpler, more predictable approach—even if it means trusting a C compiler. There’s curiosity about how BIO stacks up to the retro Parallax Propeller, a link to earlier debates, and bunnie’s own cameo—“time zones strike again”—triggering the classic “OP in the thread” meme. Jokes fly about Bao vs. Pi and “side-set with side-eye.” The vibe: half intrigued by BIO’s clean design, half defending Pi’s PIO as proven in real silicon. Drama served hot, with extra GPIOs.
Key Points
- •BIO is an I/O co-processor integrated into the mostly open-source 22nm Baochip-1x SoC, with code examples provided in assembly and C.
- •The article studies Raspberry Pi’s PIO as a reference: four processors, nine instructions, and a 32-instruction memory enabling cycle-accurate GPIO control.
- •A PIO clone (based on Lawrie Griffith’s fpga_pio) was implemented and tested; on an XC7A100 FPGA it consumed over half the device and had timing closure issues.
- •Each PIO core used about 5,000 logic cells, exceeding a VexRiscv CPU core (~4,600 without caches); VexRiscv met 100MHz timing, while PIO struggled at 50MHz.
- •Timing analysis indicated complex, CISC-like instructions in PIO contribute to long combinational paths, informing BIO’s design approach.