April 5, 2026
Open chip, open can of worms
Aegis – open-source FPGA silicon
Open chip goes from code to factory; fans swoon, skeptics ask “but can it talk fast”
TLDR: Aegis claims a fully open reprogrammable chip, from design to factory, aiming for truly inspectable hardware. Commenters split between “shut up and take my money,” doubts about missing high-speed connections, and a name-clash chuckle—while security folks celebrate an auditable silicon path that could boost trust in hardware.
The open-hardware crowd just got a new crush. Aegis promises a reprogrammable chip (an FPGA) that’s open from top to bottom—design files, tools, even a path to real silicon via wafer.space and the Sky130 open chip process. Translation: you can inspect the guts, not just the wrapper. Cue the cheers—one user basically yelled “shut up and take my money,” while another called it a huge win for trust, saying it’s the first time the actual chip fabric is auditable. Security-minded folks are swooning.
But this is the internet, so the confetti landed on a debate. A veteran warned that open FPGAs often flop on the “talking to the outside world” part—missing fast lanes like high-speed serializers and fancy memory pins. Drama alarm! Aegis’s spec lists a SerDes block (the speedy in/out bit), and commenters rushed in to note it, turning the thread into a mini fact-check brawl: is this finally the open chip that can keep up, or just another science fair project?
Meanwhile, a side plot: name collision. There’s already an open-source Aegis Authenticator app. Cue jokes about two-factor “Aegis-ing” your Aegis. Bottom line: the hype train is leaving the station, powered by open tools (like Yosys and nextpnr) and a real tapeout pipeline—now everyone’s watching to see if those fast ports deliver.
Key Points
- •Aegis is a fully open-source FPGA platform with open fabric and toolchain, aiming for real silicon via open PDKs and wafer.space.
- •The first device, Aegis Terra 1, targets GF180MCU and provides ~2,880 LUT4s, 128 BRAM tiles, 64 DSP tiles, 224 I/O pads, 4 SerDes, and 2 clock tiles.
- •A complete toolchain is provided: Yosys for synthesis, nextpnr for place-and-route, a device packer for bitstreams, and a simulator for bitstream-based testing.
- •The ASIC tapeout pipeline uses Yosys and OpenROAD to generate netlists, DEF, and GDS2, with timing and power reports; supports GF180MCU and Sky130 PDKs.
- •The fabric is generated by ROHD (Dart) to SystemVerilog, follows Xilinx-style CLB/tile conventions, and uses a serial configuration shift chain.