April 28, 2026
Silicon, sarcasm, and robot hustle
Show HN: Auto-Architecture: Karpathy's Loop, Pointed at a CPU
AI tinkered with a tiny computer chip and the comments instantly turned into a brawl
TLDR: An AI system repeatedly edited and tested a small chip design, ending up much faster than its starting point and even beating a well-known human-tuned baseline. Commenters were impressed but divided: some said the real hero was the tough testing system, while others mocked the AI-written vibe and warned this could become a game of “who passes the checker best.”
A hacker pointed an AI "research loop" at a simple computer chip design and, in under 10 hours, it kept trying changes, testing them, and saving only the winners. The result was a big speed jump: roughly 92% better than the starting version, and even better than a respected human-tuned rival on this benchmark. That alone is headline bait. But on Hacker News, the real action was the comment section, where people immediately split into camps: "this is huge", "this is just a fancy genetic algorithm", and "why does the write-up sound like the AI ghostwrote it?"
One of the strongest reactions came from users saying the secret sauce wasn't the chatbot genius at all — it was the strict referee. Every AI change had to survive formal checks, simulator tests, and real hardware placement before it could stay. As one commenter basically put it, the verifier is the star, not the vibes. Others were more suspicious, poking fun at the article's polished machine-like tone and wondering how much human cleanup was hiding behind the curtain.
Then came the philosophy and doomposting. One commenter dragged in Stanislaw Lem from 1964 to say, essentially, called it. Another cracked that if AI can satisfy any written rule faster than a team, the next startup boom will be a "verifier verifier" industry. Funny, but also a little chilling: if machines get amazing at passing tests, what happens in medicine, finance, or anywhere the tests matter most? The chip got faster, sure — but the comments turned it into a referendum on whether AI is clever, overhyped, or simply very good at gaming the scoreboard.
Key Points
- •The article describes applying an autonomous propose-implement-measure-keep loop to CPU microarchitecture using a 5-stage in-order RV32IM core in SystemVerilog.
- •The orchestration is fixed, while each round uses hypothesis generation, isolated RTL edits, and an evaluation pipeline combining riscv-formal, Verilator cosimulation, nextpnr place-and-route, and CoreMark validation.
- •A locked baseline of 2.23 CoreMark/MHz and 301 iter/s was compared with VexRiscv's published 2.57 CoreMark/MHz at 144 MHz.
- •Across 73 hypotheses over 9 hours and 51 minutes, the system produced 10 accepted improvements, 50 regressions, 9 formal/cosim failures, and 4 placement failures.
- •The final reported design reached 2.91 CoreMark/MHz, 577 iter/s, 199 MHz Fmax, and 5,944 LUT4, which the article says exceeds both its baseline and the cited VexRiscv comparison.