June 1, 2026
Stacked, packed, and getting hot
A new way to build chips: Sequentially stacking silicon to extend Moore's Law
Chipmakers want to build upward, but the comments are already overheating
TLDR: Researchers say they’ve found a practical way to stack silicon chips vertically, a big deal because shrinking parts on flat chips is hitting physical limits. Commenters immediately turned it into a heat drama, joking about nuclear-reactor temperatures, fourth-dimension cooling, and whether this is just old ideas in tiny form.
The big news: researchers at the University of Illinois say they’ve found a way to stack silicon chip layers on top of each other without frying the delicate wiring underneath. In plain English, instead of making computer parts endlessly smaller, they want to build them like tiny apartment towers. That could mean faster computers, less wasted energy, and a possible lifeline for Moore’s Law — the long-running idea that computers keep getting more powerful over time.
But in the comments, the real show was the instant panic over heat. One reader cut straight to the nightmare scenario: if chips are already blazing hot, what happens when you stack them like techno-lasagna? Another brought in legendary chip designer Sophie Wilson’s infamous line about active silicon getting hotter than a nuclear reactor, which is exactly the kind of quote that makes a science story feel like a disaster movie. Suddenly the breakthrough had a villain: thermal meltdown.
Then came the joke squad. One commenter proposed the obvious solution: just use a fourth dimension to dump the heat, which is honestly the most internet way possible to solve physics. Another compared the whole thing to old-school cordwood construction, basically asking whether the future of computing is just retro electronics with better branding. So yes, the researchers landed a serious Nature paper with eye-popping yields, but the crowd response was a mix of awe, skepticism, and "cool story, now explain how it won’t cook itself."
Key Points
- •Researchers led by Qing Cao demonstrated a scalable process for sequentially stacking high-performance silicon circuits for monolithic 3D chips.
- •The article positions vertical silicon stacking as an alternative to continued transistor shrinking as conventional chip scaling nears physical limits.
- •A major challenge in monolithic 3D integration is staying within a 400°C thermal budget for upper layers, compared with roughly 1,000°C processes used for high-quality silicon fabrication.
- •The team reported using single-crystalline silicon while achieving 98–100% device yields in an academic cleanroom.
- •The study was published in Nature, and the researchers are preparing to translate the process to an industrial semiconductor foundry with support from a center partnered with IBM, Intel, and TSMC.