June 23, 2026
Chip skyscraper chaos
Samsung Demonstrates 3D Stacked FETs with Triple Nanosheet Channels at 42nm
Samsung’s chip tower stuns fans, but commenters are already yelling about the heat
TLDR: Samsung unveiled a way to stack key chip parts vertically, a major step toward fitting more power into the same space and one of the top-rated research reveals of the year. Commenters were torn between awe at the manufacturing feat and anxiety that all that extra density could mean even more heat trouble.
Samsung just showed off a new way to pack more computing power into the same tiny space: instead of placing chip parts side by side, it stacks them on top of each other, like turning a crowded suburb into a skyline full of high-rises. The research was a big deal at the 2026 VLSI Symposium, where it scored near the top out of more than 1,000 papers and even snagged Best Paper status. In plain English: Samsung is trying to keep shrinking and improving chips by building upward, not just squeezing things tighter on a flat surface.
But the real show was in the comments, where the community instantly split into two camps: “this is amazing” and “cool, but won’t it cook itself?” RicoElectrico came in with the most relatable concern possible — heat — basically asking whether stacking more stuff together is just a fancy way to make a tiny expensive toaster. Meanwhile, armitron went full hype mode, suggesting this could speed up the road to ultra-small future chips much sooner than expected. And then there was the classic internet energy: one user casually dropped a Wikipedia link to explain what a transistor is, while another seemed delightfully hypnotized by Samsung’s city-building analogy. The biggest nerd-awe moment came from mschuster91, who marveled that this level of precision across huge 300mm wafers and dozens of manufacturing steps is “an insane achievement on its own.” So yes, Samsung brought the science — but the comment section brought the suspense, skepticism, and memes-in-waiting.
Key Points
- •Samsung Electronics’ Semiconductor Research Center presented a paper at the 2026 VLSI Symposium demonstrating 3D stacked FETs at a 42 nm gate pitch with triple stacked nanosheet channels.
- •The paper received a review score of 8.29 out of 10, ranked among the highest-scoring papers out of more than 1,000 submissions, earned Best Paper recognition, and was included in the symposium’s Technical Highlights and Press Kit.
- •The article explains that continued logic scaling depends not only on better transistor control but also on more efficient placement of n-type and p-type transistors.
- •3D Stacked FETs are described as vertically stacking n-type and p-type transistors, allowing higher transistor density within the same chip footprint than conventional planar side-by-side layouts.
- •The article identifies three main implementation challenges for 3D stacked FETs: securing sufficient current conduction paths, uniformly forming multiple high-quality channel layers, and electrically isolating the upper and lower transistors.